This invention relates to a field effect transistor and in particular to the structure of a field effect transistor, which is suitable for active matrix addressed liquid crystal display.
As a thin film field effect transistor (hereinbelow abbreviated as TFT) for liquid crystal display the matrix control is easier and it is possible to obtain a display having a higher quality with increasing on/off-current ratio. The on-current is determined principally by the size of the TFT and the field-effect mobility in the channel region. It is believed that the off-current is determined principally by the size of the TFT, and the resistivity and the crystallinity of the semiconductor layer constituting the channel region, but beside them it includes a component determined by the quality of the p-n junctions between the source and drain regions and the channel region.
Next, problems in the prior art techniques will be concretely explained by using an example illustrating the construction of a prior art TFT indicated in FIG. 1 and an example of its drain current (I.sub.D)-gate voltage (V.sub.G) characteristics. As indicated in FIG. 1, an n.sup.+ source region 3 and an n.sup.+ drain region 4 are formed in a non doped polycrystalline Si layer disposed on an insulating substrate 1 by the ion implantation method. A gate insulating film 5 and a gate electrode 6 are disposed right above a channel region 2, where no ions are implanted. When a voltage V.sub.G &gt;0 is applied to the gate electrode 6, the surface portion 200 of the channel region 2 right below the gate insulating film 5 is changed into n conductivity type and a drain current I.sub.D flows between the source region 3 and the drain region 4. On the contrary, when a voltage V.sub.G &lt;0 is applied thereto, the surface portion 200 is changed into p conductivity type and consequently no drain current I.sub.D should flow therebetween, as indicated by the curve (a) in FIG. 2. However, in reality, a current as indicated by the curve (b) in FIG. 2 flows therebetween. This is because the electric field at the interface 201 of the drain junction, which is reverse biased, increases with increasing V.sub.G, which increases the leak current through this junction. In the case where a TFT is formed wholly with a monocrystal, since it is possible to form a drain junction having a good crystallinity leak current through this junction is negligibly small. On the contrary, in the case where a TFT is formed with polycrystalline Si, amorphous Si, etc., since there exist a number of trap levels at grain boundaries at the neighborhood of the junction, leakage current therethrough cannot be neglected. This means substantially that the on/off-current ratio is reduced and thus such a TFT is not preferable for the liquid crystal display.
Such a problem is provoked also in the case where a voltage V.sub.D is applied to the source region and the drain region is grounded. Concerning this problem, in Japanese Journal of Applied Physics Vol. 21, No. 10, 1982 pp. 1472-1478, it is discussed that in a usual coplanar type polycrystalline Si TFT, where the source region (S) and the drain region (D) are formed at the two ends, respectively, leakage current is extraordinary great, when a reverse voltage is applied to the gate, and this is provoked by junction breakdown of the drain region due to crystalline imperfection in polycrystalline silicon. JP-A No. 58-171860 can be cited as a publication disclosing measures for solving this problem, where among a plurality of TFTs at least two of them are connected in series, whose gate electrodes are connected in common so that they work as if they were a TFT. Therefore the device disclosed in the publication has a problem that integration is difficult because of a large number of necessary transistors.